The present disclosure relates to a phase-locked circuit and a radio communicating device that include a calibration circuit having a voltage correcting function for supplying an appropriate calibration voltage to a voltage controlled oscillator.
In an RF transceiver, a frequency synthesizer may now be essential as a local oscillator that can achieve a highly accurate output frequency.
FIG. 1 is a diagram showing a typical configuration of an RF transceiver.
FIG. 2 is a diagram showing a typical configuration of a PLL (frequency synthesizer) in FIG. 1.
The RF transceiver 1 of FIG. 1 has an antenna 2, a low noise amplifier (LNA) 3, a power amplifier (PA) 4, filters 5 and 6, mixers 7 and 8, and a phase-locked circuit (PLL: Phase Locked Loop) 9 as a frequency synthesizer.
The PLL 9 of FIG. 2 has a phase comparator (Phase Frequency Detector: PFD) 10, a charge pump (CP) 11, and a loop filter (LF) 12.
The PLL 9 further includes a voltage controlled oscillator (VCO) 13 and a frequency divider (N) 14.
Because the RF transceiver 1 needs a high-precision modulating and demodulating clock, an LC-VCO using an inductor L and a capacitor C is typically used as the VCO in FIG. 2.
FIG. 3 is a diagram showing a typical configuration of the LC-VCO.
As shown in FIG. 3, the LC-VCO includes an inductor L, an offset capacitance COS, a varactor capacitance CVAR, a transistor TR for realizing a negative resistance, and circuit bias resistances RTOP and RBTM.
In this case, a terminal TVCTL and a terminal TOUT in FIG. 3 respectively represent a terminal TVCTL and a terminal TOUT in FIG. 2.
An operation of the PLL using the LC-VCO as the VCO 13 will be briefly described in the following.
First, the PFD 10 detects a phase difference between a reference signal REF and a signal FB obtained by frequency-dividing the output OUT of the PLL 9 as phase difference information, and passes the phase difference to the CP 11.
The CP 11 sends a current corresponding to the phase difference into the LF 12. The LF 12 converts the current into voltage information. The VCO 13 receives the voltage VCTL. The VCO 13 changes the capacitance of the varactor capacitance CVAR, and thereby changes oscillation frequency.
The feedback is thus performed until the phases (frequencies) of the reference signal REF and the signal FB become identical with each other. A clock synchronized with the reference signal REF is thereby generated.
FIG. 4 is a diagram showing the control voltage versus frequency characteristic of the LC-VCO.
In general, the variable range of oscillation frequency of the LC-VCO is about twofold at most in terms of practical performance. The frequency is changed as indicated by a reference A in FIG. 4.
This is realized by providing the varactor capacitance CVAR and the offset capacitance COS for a few bits, changing the capacitances stepwise (digitally), and changing the capacitances between steps continuously (in an analog manner) by the varactor capacitance CVAR.
Although a characteristic as indicated by a reference B in FIG. 4, for example, is also conceivable, it is difficult to realize the characteristic by an LC-VCO. Even if the characteristic can be realized, the voltage versus frequency conversion gain Kvco of the VCO 13 is increased.
When the voltage versus frequency conversion gain Kvco is increased, the current noise of the CP 11, the resistance noise of the LF 12, and the like are multiplied by the voltage versus frequency conversion gain Kvco, and are converted into the output phase noise of the VCO 13.
Thus, a low voltage versus frequency conversion gain Kvco is generally desirable, and phase noise design for the whole of the PLL can be relaxed by decreasing the voltage versus frequency conversion gain Kvco as much as possible.
That is, the oscillation frequency is generally changed as shown by characteristic curves A in FIG. 4. Even so, a wide frequency range can be covered by a low voltage versus frequency conversion gain Kvco.
One covered frequency range switched digitally will be referred to as a “band.”
It is very important in this case to provide frequency redundancy between bands. This frequency redundancy will be referred to as a “band overlap.”
This band overlap will be defined also for later description.
FIG. 5 is a diagram of assistance in explaining the definition of the band overlap.
Directing attention to a band Band1 shown in FIG. 5, because a band overlap is a frequency redundancy between two bands, there are a band overlap BOLH between the band Band1 and a band Band2 and a band overlap BOLL between the band Band1 and a band Band0.
The band overlap BOLH is defined as a margin possessed with respect to an intermediate frequency F12c between the respective frequencies F1 and F2 of the bands Band1 and Band2 at a frequency calibration voltage Vcal.
Specifically, the band overlap BOLH is a margin possessed by an oscillation frequency F1h when a maximum control voltage Vdrh is given to the band Band1 with respect to the intermediate frequency F12c. The band overlap BOLH is expressed as follows.
                              B          ⁢                                          ⁢          O          ⁢                                          ⁢          H          ⁢                                          ⁢          L                =                                            (                                                F                  ⁢                                                                          ⁢                  1                  ⁢                  h                                -                                  F                  ⁢                                                                          ⁢                  12                  ⁢                  c                                            )                                      F              ⁢                                                          ⁢              1              ⁢              c                                ×                      100            ⁢                                                  [            %            ]                                              [                  Equation          ⁢                                          ⁢          1                ]            
In this case, the intermediate frequency F12c is obtained by the following equation.
                              F          ⁢                                          ⁢          12          ⁢          c                =                                            F              ⁢                                                          ⁢              2              ⁢              c                        +                          F              ⁢                                                          ⁢              1              ⁢              c                                2                                    [                  Equation          ⁢                                          ⁢          2                ]            
Similarly, the band overlap BOLL is defined as a margin possessed with respect to an intermediate frequency F01c between the respective frequencies F0 and F1 of the bands Band0 and Band1 at the frequency calibration voltage Vcal.
Specifically, the band overlap BOLL is a margin possessed by an oscillation frequency F1min when a minimum control voltage Vdrl is given to the band Band0 with respect to the intermediate frequency F01c. The band overlap BOLL is expressed as follows.
                    BOLL        =                                            (                                                F                  ⁢                                                                          ⁢                  01                  ⁢                  c                                -                                  F                  ⁢                                                                          ⁢                  11                                            )                                      F              ⁢                                                          ⁢              1              ⁢              c                                ×                      100            ⁢                                                  [            %            ]                                              [                  Equation          ⁢                                          ⁢          3                ]            
The intermediate frequency F01c is obtained by the following equation.
                              F          ⁢                                          ⁢          01          ⁢          c                =                                            F              ⁢                                                          ⁢              1              ⁢              c                        +                          F              ⁢                                                          ⁢              0              ⁢              c                                2                                    [                  Equation          ⁢                                          ⁢          4                ]            
Without the band overlap, the PLL cannot be frequency-locked when a target frequency falls exactly in a frequency gap between the bands.
However, obtaining a large band overlap is equivalent to raising the voltage versus frequency conversion gain Kvco, and there is a tradeoff between the obtainment of a large band overlap and PLL phase noise design. Thus, there is generally a desire to design as small a band overlap as possible.
The voltages Vdrh and Vdr1 in the above description are respectively the maximum value and the minimum value of an output dynamic range where the CP can ensure performance.
Thus, a variable frequency range is limited by the voltages. Therefore, when similar frequency change is realized by the same number of bits in an advanced low-voltage process, the voltage versus frequency conversion gain Kvco is raised, and design becomes stringent.
Further, there may be a desire to achieve locking to a target frequency as a system requirement specification, and perform fine tuning by varying the frequency by plus or minus a few percent. The band overlap is an important index also in such a case.
Because a covered frequency range is limited by a band as in the above description, an appropriate band needs to be selected so that the PLL is locked to a target frequency, and frequency calibration needs to be performed.
Thus, as shown in FIG. 6, a circuit for performing the frequency calibration is necessary in addition to the PLL proper.
FIG. 6 is a diagram showing the PLL proper and the calibration circuit.
The calibration circuit 20 has a frequency counter (FC) 21, a target frequency storage circuit (REGTG) 22, and a counter value retaining circuit (REGFC) 23 for retaining a counter value of the frequency counter.
The calibration circuit 20 has a comparator circuit (COMP) 24 for comparing a target frequency with a value counted by the FC 21.
The calibration circuit 20 has a control circuit (CTL) 25 for determining a result of the comparison of the COMP 24 and supplying a control signal to the VCO 13 and a bias circuit (VBIAS) 26 for supplying a voltage to a control voltage terminal of the VCO 13.
FIG. 7 is a diagram showing a typical calibration sequence.
A typical calibration sequence will next be described with reference to FIG. 7.
First, the CTL 25 shown in FIG. 6 outputs a control signal SCTL so that the VCO 13 oscillates at a lowest frequency, and the VBIAS 26 supplies a control voltage value (ST1).
In this case, N denotes an SCTL code, and a state is assumed in which all the capacitances are set in an ON state and the oscillation frequency becomes lowest by maximizing N. In this state, an external reference clock REFCLK is set to a specified count time, and the FC 21 counts the oscillation frequency of the VCO 13 (ST2).
The COMP 24 compares a result of the count of the FC 21 with a target frequency retained in the REGTG 22. When the result of the count of the FC 21 is lower than the target frequency, the result is retained in the REGFC 23. The CTL 25 changes the control signal SCTL again, and controls the control signal SCTL so as to increase the oscillation frequency of the VCO 13. The above sequence is repeated until the oscillation frequency exceeds the target frequency.
When the oscillation frequency exceeds the target frequency, a comparison is made to determine which of the present count value and a count value in an immediately preceding state which count value is retained in the REGFC 23 is closer to the target value, and a band to be used is determined. The calibration sequence is then ended.
It is very important in this frequency calibration not to select a wrong band.
A wrong band selection is made due to relation between the voltage supplied at the time of the calibration which voltage is represented by VCTL in FIG. 6 and the oscillation frequency of the VCO.
FIGS. 8A and 8B show an example of this phenomenon.
FIGS. 8A and 8B are diagrams showing a control voltage versus frequency characteristic of the VCO, the diagrams being of assistance in explaining an error in frequency calibration by calibration voltage.
FIG. 8A shows an example of a calibration success.
In this example, there is a calibration voltage Vcal exactly midway between the upper limit Vdrh and the lower limit Vdrl of the control voltage of the VCO 13, and each band is symmetric with respect to an intersection with the calibration voltage Vcal between the limits Vdrl and Vdrh.
Suppose that there is a target frequency Ftg as indicated by a line X for two bands Band1 and Band2. In addition, frequencies when the calibration voltage Vcal is given to the bands Band1 and Band2 are denoted as F1c and F2c, respectively, and an intermediate frequency of the frequencies F1c and F2c is Fc.
From the above description of the calibration sequence, because Ftg<Fc, the calibration circuit selects the band Band1.
Thus, the calibration sequence is ended. When the PLL is operated, the control voltage for the PLL changes, and the PLL is locked to the target frequency Ftg with Vctl=Vlf. At this time, it is shown that a frequency F1h is sufficiently higher than the target frequency Ftg, and that there is a margin.
On the other hand, FIG. 8B shows an example of a calibration error.
In this example, the relation between the voltages Vdrl, Vcal, and Vdrh is the same, whereas each band is asymmetric with respect to the calibration voltage Vcal between the limits Vdrl and Vdrh.
From FIG. 8B, Ftg<Fc. Thus, the frequency calibration circuit 20 selects the band Band1. Even when the calibration sequence is ended to proceed to PLL operation, the control voltage is changed, and the maximum frequency F1h of the band Band1 is reached, the target frequency Ftg is not reached.
That is, in the case where frequency calibration is performed by the calibration voltage Vcal shown in FIG. 8B, the PLL cannot be locked to the target frequency Ftg, and the wrong band is selected.